A. Field of the Invention
The present invention relates to an interpolating D/A architecture for integrating a large number of D/As on a single chip, especially to an interpolating D/A architecture for a TFT-LCD source driver integrating a significant number of such D/As to reduce the cost of the driver IC.
B. Description of the Prior Art
A TFT-LCD Thin Film Transistor-Liquid Crystal Display source driver is a circuit that supplies video signals to an LCD pixel array. Refer to FIG. 1 for showing the structure of a conventional TFT-LCD source driver 10 with 384 output channels 101, each with an 8-bit resolution. A shift control register 108 is a bi-directional shift register, which sequentially enables the data registers 104 from the left side or the right side in response to the DIOL signal or the DIOR signal. A 48-bit input bus DIN[1-48], strobed synchronously by the rising edge of the SCLIK 109 signal, is used to serially load the 384 internal data registers 104. On each rising edge of the SCLK 109 signal, 6 data registers will be filled. After all of the data registers 104 are loaded, the contents of the data registers 104 are transferred to the data latches 105 when the LAT signal 107 is high. The outputs of the data latches 105 are converted by 384 8-bit digital to analog (D/A) converters 102 to drive the pixel arrays 106. Since the source driver 10 needs a large number of D/A converters 102, the area of the D/A converters 102 constitute a major portion of the overall cost budget of the source driver 10.
FIG. 2 shows a more detailed block diagram of a prior art implementation of the D/A converters 102. It consists of a reference voltage generator 21, a decoding switch network 22, and an output buffer 103. The reference voltage generator 21 is shared among all outputs to save area. For an 8-bit D/A converter, 255 resistors are used to generate 256 reference levels as shown in FIG. 3. The resistances in the reference voltage generator 21 are not necessarily equal in value. Typically, they are carefully chosen so that the generated reference levels form a gamma-corrected transfer curve. The 256 global reference levels are typically routed with 256 horizontal metal lines over the decoding switch network 22. The decoding switch network 22 consists of 256 rows of switches 31, each with 8 serial transistors 32 as shown in FIG. 4. One of the 256 rows of switches 31 will connect the selected reference level to the output buffer 103. The schematic of a conventional output buffer 103 is shown in FIG. 5.
The major problem in the conventional source driver is the complexity and size of the decoding switches. The number of the horizontal metal lines and the number of rows of the serial switches 31 are so large that they usually occupy significant amount of die area, and therefore play a major role in determining the total cost of the chip. Moreover, conventional TFT applications with output polarity control need two sets of reference voltages, thus requiring 512 metal lines for an 8-bit resolution. With such an implementation, the D/A section will take up 1/3 of the overall chip area.